1. Field of the Invention
The present invention relates to a fabricating method of multi-layered interconnections. More particularly, the present invention relates to a method of fabricating a dual damascene structure.
2. Description of the Related Art
Due to the increased number of devices incorporated in a semiconductor circuit and the corresponding size reduction of the devices, material property is an important factor that affects device performance. For example, the material of the metallic multi-layered interconnections greatly affects resistance of the devices. Thus, in order to reduce the resistance, it is an important subject to select a suitable metallic material.
Copper has many good qualities such as a low resistivity and a high electromigration resistance. In addition, copper can be formed by chemical vapor deposition (CVD) or electroplating. Thus, copper is widely used in sub-micron process to form multi-layered interconnects. However, some problems still occur when using copper in sub-micron process. For example, copper is easily oxidized and eroded. It is difficult to pattern copper by dry etching. The adhesion between copper and dielectric materials is poor. Furthermore, copper easily diffuses into the dielectric materials so that the reliability of devices is decreased.
To solve the above-described problems, the conventional method uses a dual-damascene technique with a chemical-mechanical polishing step. FIGS. 1A through 1C are schematic, cross-sectional views showing a conventional method of fabricating a dual damascene structure. A dual-damascene technique is a technique that forms a metallic interconnection 114 (FIG. 1B) in a dielectric layer 106. In FIG. 1A, a dielectric layer 106 is first formed over a substrate 100, and then the dielectric layer 106 is planarized. According to the required design, the dielectric layer 106 is then patterned. A trench 108 and a via hole 110 are formed to expose a portion of the conductive layer 102. In FIG. 1B, a barrier layer 112 is formed over the substrate 100. A copper layer 114 is formed over the substrate 100 to fill the trench 108 and the via hole 110. A conductive line and a via contact are thus simultaneously formed.
The barrier layer 112 having a high stability is used to solve the above-described problems, such as copper atom diffusion and poor adhesion between the copper layer 114 and the dielectric layer 106. As shown in FIG. 1C, a chemical-mechanical polishing (CMP) step is performed. Because it is difficult to etch the copper layer 114, the conventional method solves this difficulty by using the CMP step instead of performing an etching step. Thus, the difficulty in etching the copper layer 114 does not occur.
Typically, the material of the barrier layer 112 in the dual damascene structure is tantalum/tantalum nitride (Ta/TaN). Because it is difficult to remove the Ta/TaN layer by chemical-mechanical polishing, the dual damascene structure is still formed with difficulty. In order to remove the barrier layer 112, it is necessary for the conventional method to perform an over-polishing step. Since the etching rate for the Ta/TaN barrier layer 112 is lower than that of the copper layer 114, the copper layer 114 is easily dished or suffers from an erosion problem. Thus, the process is still not optimal.